The present invention is converned with improving the access time to memory cells in a random access memory. The preferred embodiment described herein deals with circuitry implemented on a 64K CMOS static RAM.
Some of the delays in reading a memory cell in a static RAM comprise the cell-select time which corresponds to the time required to operate the address buffer and decoder followed by the word line delay. A subsequent delay is the cell-read time which corresponds to the time required for the sense amplifier and output buffer operation. In a 16K static RAM, the cell select time as defined is about 68% of the total delay and the cell-read time is the remaining 32%.
As static RAM density is increased, the cell-read time has become a larger percentage of the total access time. Considering a 64K static RAM, the cell-select time is about 58% and the cell-read time is about 42% of the total. Reasons for this increased percentage of total delay attributed to the cell-read time are that the bit line signal is reduceed due to weaker memory cell transistors and there is a larger bit line capacitance.
The principal object of the present invention is to reduce the cell-read time.